Random access memory (RAM) can be utilized in computer platforms for temporary data storage in main memory. In particular, dynamic RAM (DRAM) memories provide a cost effective solution for system memory. An improvement on DRAM resulted in synchronous DRAM (SDRAM) technology where a synchronous interface is used to access memory data. That is, data from memory is transferred on the rising edge of clock pulses that are synchronous with the computer system bus and processor. In particular, SDRAM transfers one bit (per data line) of data per clock cycle.
An improvement of SDRAM resulted in “Double Data Rate” (DDR) SDRAM technology. Basically, DDR technology doubles the bandwidth, or data rate transfer, of SDRAM. In particular, DDR memories transfers data on both the rising (from low to high) and falling (from high to low) edges of a clock cycle. As such, two bits (per line) of data are transferred for each clock cycle. The evolution of DDR memories resulted in DDR2 memories where the bandwidth, or data rate transfer, of DDR memories is doubled. Moreover, higher data rate transfer can be achieved in DDR2 memories.
DDR memories are sometimes used in low power devices (e.g., LP-DDR, LP-DDR2, etc.). These smaller low power devices (e.g., cell phones, personal digital assistants (PDAs), mobile devices, etc.) greatly benefit from the higher access speeds of DDR technologies while operating under low power conditions.
Two issues greatly influence low power LP-DDR timing. Firstly, LP-DDR read data timing requires the client chip to predict a window in time when return read data is received. Secondly, the client must also delay the return clock strobes so that they can sample data at a stable time. Both problems are usually addressed with tunable delays in the client circuitry. Typical solutions are either static delay chains or delay lock loops (DLLs) whose power consumption is not amenable to the low power market.
Process-voltage-temperature (PVT) variations can greatly affect performance of the LP-DDR memories. PVT variations can become very large. For example, a mobile application may experience extreme temperature variations. That is, in a mobile market, operating conditions can also see a large variance.
In particular, access to data in the DDR memories is implemented through the use of a read strobe (clock) supplied by the DDR memory. The read strobe is closely aligned with the data coming from the memory. That is, the rising and falling edges of the read strobe coincide with the incoming data byte strobes coming from the DDR memory. For example, data is read when the read strobe is switching and a “quse” signal (e.g., a signal indicating that the Q output of the memory is expected to be in use) is high.
However, data cannot be sampled when the data is switching with the read strobe. As such, the read strobe is delayed so that data can be accessed when the data is not switching. In particular, up to a certain frequency, trimmer delays can be done statically by selecting a delay through a fixed and unchanging number of logic cells throughout the course of operation of the device. Additionally, the cell chain is susceptible to PVT variance, and therefore finding a static trimmer value that adapts to all conditions of operation is difficult. For example, mobile applications can experience extreme temperature variations, resulting in large PVT variance. As PVT conditions vary towards the extreme, a static trimmer value will gradually lose its centering property as the delay cells diverge from their nominal delay. As such, reduced operating frequencies are implemented to account for PVT variations.
As previously mentioned, DLLs can be implemented to obtain invariant delays in the read strobe. However, DLLs are known to consume large amounts of power, and therefore may not be suitable for mobile applications which operate under severe low power restrictions. Compared to typical DDR memories, the absence of a DLL on the LP-DDR memories causes a large variance on the return time of read data. Since the tunable delays of the receive circuitry are not matched in the LP-DDR, this requires the circuitry for the tunable delays to be as invariant as possible under all operating condition. However, in low power, mobile DDR applications, the PVT variance is even more pronounced since the tAC timing parameter, common to most DRAM memories, has almost a full clock cycle of variance due to the absence of DLLs.